`timescale 1ns/1ns
`define DIVIDER 14'd9999

module test();
  reg clk_48; 
  reg rst;
  wire tx;
  wire rd;
  wire dtr, dsr, cd, rts, cts, wren, clk2, resout;
  wire [15:0] data;
  wire [10:0] addr;
  hyperterm hyp(
    .clk_48(clk_48),
    .rst_(rst),
    .tx(tx),
    .rd(rd),
    .dtr(dtr),
    .dsr(dsr),
    .cd(cd),
    .rts(rts),
    .cts(cts),
    .data(data),
    .addr(addr),
    .wren(wren),
    .clk2(clk2),
    .resout(resout)
  );
  wire dtr2, dsr2, cd2, rts2, cts2;
  hyperterm2 hyp2(
    .clk_48(clk_48),
    .rst_(rst),
    .tx(rd),
    .dtr(dtr2),
    .dsr(dsr2),
    .cd(cd2),
    .rts(rts2),
    .cts(cts2)
  );
  wire [15:0] q;
  ram_2048x16_1p RAM (
    .address(addr),
    .clock(clk_48),
    .data(data),
    .wren(wren),
    .q(q)
  );
  initial begin
        clk_48 <= 1'b0;
        rst <= 1'b1;  
    #250 rst <= ~rst;
    #500 rst <= ~rst;
  end
  always #1
    clk_48 <= ~clk_48;
endmodule